The invention relates generally to computer systems, and deals more particularly with manipulation of storage protection keys within a two level cache system. The keys are used to regulate access to associated pages of main memory.
Most computer systems include a main memory and a cache system to expedite access to main memory data. A typical cache system comprises a data cache to store data fetched from or written to main memory, and a directory to store "absolute" addresses of the data copied into the data cache. The absolute addresses are the actual main memory addresses. The processor can access the data cache faster than the main memory because the data cache is smaller than the main memory, located closer to the processor than the main memory, and usually formed from faster but more expensive technology. An effective caching strategy relies on spatial and temporal locality of reference, i.e. the data likely to be needed next by the processor is stored in the main memory near the data currently requested. This is true, for example, when the processor requests to sequentially read a file and the words of the file are stored in successive locations in main memory. Therefore, when the processor requests data, typically four or eight bytes per access, this data along with the remainder of the cache block (typically 64, 128 or 256 bytes of contiguous addresses) are fetched from main memory and loaded into the data cache. The cost of accessing the relatively remote main memory is amortized over the return of a larger than requested block of data, relying on locality of reference to make effective use of the additional data for subsequent requests.
A hierarchical two level cache system is also known which comprises a plurality of level one (L1) data caches and respective directories, which each serve one processor, and a level two (L2) data cache and associated directory which are coupled to and serve all the L1 caches. The L2 data cache is also coupled to the main memory, retains a copy of all data requested or updated by any of the processors, and serves as a conduit for transferring data from main memory to the L1 cache of the processor which requests the data. When any processor modifies data, control hardware associated with the L2 data cache notifies all other L1 caches that their copy of the data, if stored, is now invalid.
In many computer systems, programs executing on a processor identify data by address operands embedded within an instruction. The address operands are quickly converted by hardware to a "virtual" address, a location in the program's linear address space. Then hardware, with support from the operating system, dynamically translates the virtual address to the corresponding absolute address of the location in main memory. The time required to perform the address translation is significant. Therefore, after the translation, the virtual address and the corresponding absolute or relevant portions thereof, along with program-specific control information, are stored in a translation lookaside buffer (TLB) for future reference.
In some previously known computer systems such as the IBM System/390 computers, each program does not have authority to access all of main memory. Instead, access to main memory is controlled by a storage protection key array. The storage protection key array may be stored in or stored separately from main memory, but if stored separately, is usually stored at the same level in the memory system hierarchy as main memory. Each key in the array corresponds to a 4096-byte page of main memory. When the program requests access to a page, the program must also furnish an access key, either from its program status word (PSW) or channel program key, which is then compared to the storage protection key of the addressed page. The storage protection key is composed of an access control field (4-bit value), a fetch-protection bit, a change bit and reference bit. To obtain access, the access key furnished by the program must match or master the key in the access control field. The fetch-protection bit indicates whether fetch accesses are monitored in addition to store accesses for the 4KB page. The reference bit is set whenever a fetch (read) or store (write) access is made to the page, and the change bit is set whenever the page contents are altered by the requested access. The master or privileged key is usually reserved for operating system use so that the operating system (or other bearer) can access any page in main memory regardless of the access key associated with the page.
There are different known techniques for manipulating storage protection keys in a cache system and/or TLB to expedite checking of storage protection keys. As noted-above, fetches of storage protection keys from the array in main memory are time consuming and should be avoided whenever possible to improve performance.
The prior art IBM System/390 computer system includes a two level cache system. A program executing in the system provides address operands to identify data, and then hardware converts the address operands to one or more virtual addresses. Then, the TLB is accessed to determine if the virtual address and corresponding absolute address, access control bits and fetch-protection bit are stored there. If so, the storage protection key can be checked from the TLB. If authorized, the absolute address can then be used to access the requested data from the memory hierarchy. However, if the virtual address is not currently stored in the TLB, then dynamic address translation hardware translates the virtual address to an absolute address. Following the completion of the address translation, the absolute address is used to fetch access control bits and fetch-protection bit from the storage protection key array. Finally, the virtual page address, the translated absolute page address, and the access control bits and fetch-protection bit are loaded into the TLB for the current and subsequent requests. This system provides fast address translation and fast access to the storage protection keys for subsequent requests for the same data. However, for the current request, the fetching of the storage protection key occurs after the address translation step and this delays satisfaction of the current request.
U.S. Pat. No. 3,761,883 discloses a single level cache buffer system. When a block of data is fetched into the local buffer from main memory, the storage protection key associated with that block is also fetched from the storage protection key array and stored into a key array local to the processor. This arrangement permits the key to be readily modified because the key need not be fetched again from main memory.
IBM TDB Volume 31 No.2 July 1988 pages 109-111 discloses a key array at the L2 cache level. If an access results in a miss in the L2 data cache, then the data and storage protection key are simultaneously fetched from main memory and the storage protection key array, respectively. As the main memory data is loaded into the L2 data cache, the storage protection key is loaded into the L2 key array.
A general object of the present invention is to provide storage protection keys in a two level cache with minimal overhead and fast access.